What It Is
Advanced packaging is the set of techniques for assembling multiple chips — logic dies, memory stacks, I/O chiplets — into a single package at high interconnect density. It sits at the boundary between chip design and printed circuit board assembly, enabling die-to-die bandwidth that conventional wire-bonded packages cannot achieve. Where a standard DDR5 DIMM delivers ~100 GB/s, an HBM3e stack integrated via CoWoS delivers over 1 TB/s at a fraction of the power per bit.
The key packaging technologies relevant to AI hardware are: 2.5D integration (GPU die and HBM stacks side-by-side on a silicon interposer — TSMC's CoWoS, Intel's EMIB), 3D stacking (dies bonded face-to-face at micron-scale bump pitch — TSMC's SoIC), and fan-out wafer-level packaging (dies embedded in a molded wafer for dense I/O redistribution). Each generation raises integration density and the associated yield challenges.
Why It Matters for AI Capex
The NVIDIA B200 Blackwell GPU is a CoWoS-L package. It integrates two GPU dies reticle-stitched on a 96×72mm interposer alongside eight HBM3e stacks, delivering 192 GB of memory at 8 TB/s bandwidth. Without CoWoS-L, that chip — and the revenue it generates for NVIDIA — does not exist. TSMC's CoWoS line is therefore the single most constrained node in the entire AI supply chain, more capacity-limited even than N4/N3 wafer starts.
TSMC disclosed in Q1 2025 that CoWoS-L capacity is sold out through 2026, and the company is tripling advanced packaging capacity by end-2026. This supply constraint has a direct read-through to NVIDIA's shipment cadence, Broadcom's XPU delivery schedule, and hyperscaler capex deployment timelines. Any packaging capacity announcement — from TSMC, AMKR, or the OSAT ecosystem — moves semi stocks.
Key Technologies
| Technology | Type | Key Feature | Used In |
|---|---|---|---|
| CoWoS-S | 2.5D | Standard interposer, up to 4 HBM stacks | NVIDIA A100, H100 |
| CoWoS-L | 2.5D | Reticle-stitched interposer, 8+ HBM stacks, >90mm wide | NVIDIA B200, H200, Broadcom XPU |
| SoIC-X | 3D face-to-face | <10μm bump pitch, wafer-to-wafer bonding | Future HBM4 logic base die, next-gen chiplets |
| Intel EMIB | 2.5D | Embedded bridge die, lower cost than full interposer | Intel Ponte Vecchio, Falcon Shores |
| FOPLP / FOWLP | Fan-out | Molded embedded dies, high I/O redistribution | Mobile SoCs, networking ASICs |
Supply Chain Players
The dominant advanced packaging foundry. Operates CoWoS-S and CoWoS-L lines, SoIC, and InFO (fan-out). TSMC's packaging revenue is growing faster than its wafer revenue — management has guided advanced packaging to exceed 10% of total revenue by 2027. Every NVIDIA AI GPU and Broadcom XPU flows through TSMC packaging.
Largest pure-play OSAT (outsourced semiconductor assembly and test). Amkor has been TSMC's overflow partner for CoWoS and is building its own advanced packaging lines in Arizona and Korea. Direct beneficiary of the packaging capacity crunch — AMKR's AI-related packaging revenue doubled in 2025.
Provides the deposition, CMP, and metrology tools for interposer fabrication and TSV formation. AMAT's advanced packaging segment is one of its fastest-growing businesses. The company explicitly calls out packaging as a new growth vector alongside leading-edge logic and HBM.
Lam's DRIE (deep reactive ion etch) tools form the Through-Silicon Vias (TSVs) that connect HBM DRAM layers and the interposer. Every HBM stack and CoWoS interposer requires Lam etch steps. TSV etch is among the highest-value etch applications in the entire portfolio.
Metrics to Watch
- →TSMC CoWoS wafer starts/month: Direct proxy for AI GPU shipment capacity. Management disclosed ~30k wspm in 2025, targeting 60k+ by end-2026.
- →TSMC advanced packaging revenue %: If packaging exceeds 10% of total revenue, it validates the structural mix shift away from pure wafer business.
- →AMKR AI/HPC packaging revenue: AMKR breaks out "advanced" vs. standard packaging. Rising advanced mix % signals AI demand absorption.
- →AMAT packaging equipment orders: Leading indicator — equipment orders precede capacity additions by 9–18 months.
- →CoWoS-L lead times: Reported informally through supply chain checks. Shortening lead times = easing constraint; lengthening = accelerating demand or yield issues.
- →HBM stack yield: Each HBM stack requires perfect TSV yield across 12 DRAM dies. Low yield tightens effective supply even if wafer starts are high.
Investment Signals
Bullish Triggers
- • TSMC raises CoWoS capacity guidance
- • AMKR wins new AI packaging contracts
- • NVIDIA guide above consensus (implies CoWoS demand)
- • New hyperscaler XPU design win announced
- • HBM4 ramp ahead of schedule (SoIC content)
Bearish Triggers
- • NVIDIA cuts orders (CoWoS demand proxy)
- • TSMC reports packaging yield issues
- • Export controls restrict CoWoS shipments to China
- • Alternative interposer tech delays CoWoS-L ramp
- • OSAT pricing pressure from new capacity